Huawei presented the Tau (τ) Scaling Law at the 2026 IEEE International Symposium on Circuits and Systems in Shanghai.

The company said the framework is meant to sustain semiconductor and system advances by cutting signal-propagation delay across devices, circuits, chips, and systems as Moore’s Law slows.

The framework includes new chip architecture and interconnect technologies designed to improve computing efficiency.

Huawei said it has designed and mass-produced 381 chips based on the τ Scaling Law over the past six years.

The company also plans to use LogicFolding in Kirin chips scheduled for fall 2026, and expects high-end chips it designs under the framework by 2031 to reach transistor density equivalent to 1.4nm-class processes.

Huawei’s claims do not necessarily translate directly to commercial chip manufacturing nodes.

🔗 Source: Huawei

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